As my good friend Vladimir warned me, I am posting again this question, which
continues the discussion posted as "Ordering writes in Write-Combined Memory"
of 6/4/2005.

++++++++++++++++++++++++++++++++++++++++++++++++++ ++

I will be assuming that KeMemoryBarrier() uses some kind of instruction like
MFENCE.

So, in "IA-32 Intel Architecture Software Dev Manual Vol.3: System Prog.
Guide", section 10.3.1 "Buffering of Write Combining Memory Locations" states
that
"...The only elements of WC propagation to the system bus that are
guaranteed are those provided by transaction atomicity....with a Pentium 4 or
Intel Xeon
processor, a full WC buffer will always be propagated as a single burst
transactions, using any chunk order within a transaction"

My only doubt resides in: if one of the WC buffers is full (with 64 bytes)
and the driver issues a write memory command, there will be one burst write
of those 64 bytes to the system bus, but the chunks inside this burst will be
out of order, as I understood from the text above.

Am I missing something?

"Doron Holan [MS]" wrote: