Hi,
i'm working on a AT91SAM7X-EK development board, and i'm trying to
figure out if the normal at91 watchdog behavior can be changed or
workarounded because:

"The Watchdog Mode Register (WDT_MR) can be written only once. Only a
processor reset
resets it. Writing the WDT_MR register reloads the timer with the
newly programmed mode
parameters."

due to this feature, if i disable watchdog on start up, i'm not able
to turn in on anymore until the next reset.
What i want to do is disable watchdog on startup, and then turn it on
later (on a custom received can message).
but the as the datasheet says, after writing to the register to
disable watchdog, the following command to turn it on is ignored.
what can i do? is there a way to workaround this (imho stupid)
behavior?

best regards
Andrea

The simplest solution might be:

On startup you could set the watchdog timeout to the longest possible, then
just clear it periodically with no regard for system state - maybe simply
from a timer interrupt. Then, once you have received your command to start
the watchdog monitoring for real, turn off the dummy periodic kicking and
replace it with the real watchdog functionality.


Regards,
Richard.

+ http://www.FreeRTOS.org
+ http://www.SafeRTOS.com
for Cortex-M3, ARM7, ARM9, HCS12, H8S, MSP430
Microblaze, Coldfire, AVR, x86, 8051, PIC24 & dsPIC
..... and soon AVR32

"vizzz" <andrea.visinoni@gmail.com> skrev i meddelandet
news:1172225684.379076.182620@v33g2000cwv.googlegr oups.com...
The purpose of the Watchdog is to protect against all possible failures
If you allow anyone to turn off the watchdog by mistake, then
your protection is lost.

Would like to know peoples opinion on this though.
What is the properties of a good watchdog?


--
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may not be shared by my employer Atmel Nordic AB

On Sun, 25 Feb 2007 16:44:44 +0100, the renowned "Ulf Samuelsson"
<ulf@a-t-m-e-l.com> wrote:

As non-programable as makes sense. ;-) The program once is a
reasonable compromise IMHO. Can't ever be set to more than a couple of
seconds.


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

On Sun, 25 Feb 2007 16:44:44 +0100, "Ulf Samuelsson"
<ulf@a-t-m-e-l.com> wrote in comp.arch.embedded:

My opinion is somewhat different.

One of the problems that shows up, especially with 32-bit processors
like ARM, is the fact that one might well be using an actual operating
system of some sort, and that can be a problem for watchdogs.

During the BIOS or BSP, I control the code that is executing, and I
can handle the watchdog. After the (RT)OS is initialized and running,
and it executes start up code for my tasks, I can handle the watchdog.

But in between calling the (RT)OS start up and the time when some of
my code can execute again, there can be a relatively long period,
perhaps longer than the maximum time of an on-chip watchdog.

So I want a way to turn the watchdog off, and turn it on again later.
Such a mechanism should be complicated enough so that code that is
lost due to a coding or memory error won't hit it by accident.

I see no problem with having a sequence that requires several specific
values to one or more registers being required to access the watchdog
controls, but the ability to enable or disable the watchdog, or to
change its timing, should be available at all times.

--
Jack Klein
Home: http://JK-Technology.Com
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On 26 Feb, 04:15, Jack Klein <jackkl...@spamcop.net> wrote:
I agree with Jack, this is how avr watchdog work, and want i'm doing
is a porting from atmega128.