- DMA typical times
- Posted by shrey on September 18th, 2005
Hi
I want to find out how fast DMA systems work on embedded systems ?
The purpose is to model it in a simulator. So essentially I want to
find out (roughly) given
x bytes of data how much time would the dma take? The platform I have
is a Arm processor. So Dma systems for such platforms is what I am
looking for.Can any one point me to any sources or tell me what the
typical speeds are -including the setup time.
Shrey
- Posted by Rene Tschaggelar on September 18th, 2005
shrey wrote:
Roughly clock times buswidth, so at 32bits and 100MHz, that'd be
400MBytes, if the source and the receiver are that fast.
Rene
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- Posted by larwe on September 18th, 2005
Ergh, that is leaving out too many important details. RAM bandwidth is
often the limiting factor. So it depends on the source/target of the
DMA operation, and what clock options are set for that memory. Also
depends on what the priority is between CPU and DMA, the CPU's cache
capabilities, and what the code is doing.
Essentially there is no generic answer to the OP's question.
- Posted by Rene Tschaggelar on September 18th, 2005
larwe wrote:
Sorry to not point out. My number can be considered upper limit.
RAM is a bit faster. DDR RAM get data on the falling and
on the rising edge. That'd be 800MBytes then as upper limit.
Usually peripherals, except the tuned lot (LAN, Graphics, Disk)
do not interface as 32bit.
Rene
- Posted by Keyser Soze on September 18th, 2005
"Rene Tschaggelar" <none@none.net> wrote in message
news:432dbee1$0$1163$5402220f@news.sunrise.ch...
The DMA burst transaction time of an embedded systems is usually equal to or
greater than the memory subsystem minimum cycle time.
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For more details, lean about the ARM processors you need to simulate.
Study what DMA features are implemented in each variety of processor you are
interested in.
Create the code required to initialize the DMA controller and respond to
requests for data blocks.
Study the trade offs between the type of memory subsystem (SRAM, DRAM, DDRAM
etc...), memory bus width and DMA burst transaction time to arrive at the
total system estimated DMA through put.
Now evaluate all of this and create the simulation.
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Or ... Just build one and measure it.