Hello all,

I am in the middle of laying out a design for a medical device the reads
in data pretty quickly (~20MHz) in bursts, but is limited to a slow serial
connection to transfer the data. The solution that comes to my mind is a
large FIFO buffer (~100k+) that can take an 8-bit parallel input, but I
can't find them anywhere in a reasonable price range. I've looked all over
at the common manufactures of logic devices (TI,nationalsemi) and some
distributors (digikey,mouser) but can't find much. I hear of hard drives
with 512k buffers/caches quite commonly. what am I missing here?

Does anyone know of a model/part# of a pretty high speed, 100k+ fifo
buffer?

Thanks in advance for your help.

Best Regards,
Adam Kumpf
kumpf@mit.edu
http://web.mit.edu/kumpf/www/kumpf-projects.html

Adam Kumpf <kumpf@mit.edu> wrote:

Get some fast SRAM and a CPLD/FPGA and do the FIFO by hand. There are
Cypress Dual port memory available, but they are normally hard to get in low
quantities. Well, digikey carries Cy7C009/019, but with a real proce tag...

Bye

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I agree you want to use an FPGA for this solution.
Would be very simple. If you're doing research might
look for A/D conversions as they are usually clocked
into a FIFO for holding before processing.

Terry Bowman

Uwe Bonnes wrote:

On Sunday, in article
<42347df5$0$558$b45e6eb0@senator-bedfellow.mit.edu>
kumpf@mit.edu "Adam Kumpf" wrote:
What is reasonable price range??

Often these caches are SRAM/DRAM based using some of the memory of the
hard drive or directly under ASIC control.

20MHz is not high speed for FIFOs consider looking at IDT (www.idt.com)
for their synchronous and asynchronous devices. I do assume this burst data
has some form of clock with it.

Has someone else has said a 1Mb(128KB) or 4Mb(512KB) SRAM part is easy to
find and a PLD/FPGA to drive that will be fairly trivial. Especially as the
output is slower and by the sounds of things could have its read delayed
(registered), if necessary whilst in the middle of a write cycle.

--
Paul Carpenter | paul@pcserviceselectronics.co.uk
<http://www.pcserviceselectronics.co.uk/> PC Services
<http://www.gnuh8.org.uk/> GNU H8 & mailing list info
<http://www.badweb.org.uk/> For those web sites you hate

Thanks for all of your help. The SRAM decision only slightly complicated
the design, but reduces the price drastically(by a factor of 10 or more!)...
just what I was looking for!

I'll have a microcontroller on board, so maybe I can bypass the CPLD/FPGA if
I'm clever.

Thanks again.

Best Regards,
Adam Kumpf



"Paul Carpenter" <paul$@pcserv.demon.co.uk> wrote in message
news:20050313.2002.307424snz@pcserv.demon.co.uk...

http://www.semiconductorstore.com/Pa.../Averlogic.htm

Tom Woodrow


Adam Kumpf wrote:

Be careful trying to use the processor to do the same task as the FPGA
described above. AN FPGA will typically have no latencey or delay
in servicing the output and stuffing the FIFO. These delays are often
times not guaranteed w/ a processor. If your processor can be doing
anything else, which is likely, make certain it will get the data
before
the next piece of data is ready. This all depends on the context
preemption
latency of your processor (worse case) versus the data input speed.

Also, an FPGA could be used without SRAM in some cases depending on
the size and depth of the data. This also depnds on the FPGA/CPLD used
as well. If this is possible then it could be cheaper then using SRAM
especially
if the FPGA can used for other purposes.

Terry Bowman

www.averlogic.com


"Tom Woodrow" <tomwoodrow@comcast.net> wrote in message
news:MMadncEGaoryf6nfRVn-vg@comcast.com...

Joe.G wrote:

http://www.semiconductorstore.com/Pa.../Averlogic.htm
takes you to store where you can actually buy the products. I just
bought a bunch of their FIFO chips.

Tom Woodrow