Tech Support > Computer Hardware > Microprocessors > PIC migration timing problem
PIC migration timing problem
Posted by PigPOg on June 20th, 2006


Hi, can anyone advise please?

I've migrated code running on a PIC16C54 to a PIC18F1320. Both use an
external RC network. On the OSC2 pin both processors show a nice clock
at 25 KHz (which is correct). However, the 18F1320 seems to be
executing code at twice the speed! Have I overlooked something?

Thanks in advance for any help?

Simon

Posted by Roman Ziak on June 20th, 2006


PigPOg wrote:
It's not executing the code twice speed, same C routine may generate
fewer instructions on 18Fxxx than 16Cxx and fewer instructions execute
faster. Depends on your usage of arrays and pointers but twice the speed
sounds just right.

Roman

Posted by PigPOg on June 20th, 2006


On Tue, 20 Jun 2006 07:38:55 -0400, Roman Ziak <news12@ziak.com>
wrote:

The code is written in assembly language. I can't see that this would
make a difference.

Thanks for the reply.
Simon



Posted by Robert Scott on June 20th, 2006


On Tue, 20 Jun 2006 11:25:07 +0100, PigPOg <simon@capella.co.uk> wrote:

I seem to recall that some of the higher-end PICs execute an instruction in 2
OSC clock cycles rather than the usual 4 clock cycles. Check the data sheet for
that.

Robert Scott
Real-Time Specialties

Robert Scott
Ypsilanti, Michigan

Posted by PigPOg on June 20th, 2006


On Tue, 20 Jun 2006 12:00:04 GMT, ---@--- (Robert Scott) wrote:

Thanks Robert, I'll check that out.

Simon

Posted by Spehro Pefhany on June 20th, 2006


On Tue, 20 Jun 2006 11:25:07 +0100, the renowned PigPOg
<simon@capella.co.uk> wrote:

How about your layout and bypassing? You're not using a solderless
breadboard are you? The RC capacitor lead ('Cext' in Microchip-hua)
should go directly back to a Vss pin on the micro and *nowhere else*.
At least 0.1uF ceramic in parallel with something like 10uF-100uF
electrolytic, with the ceramic especially directly across Vdd-Vss very
near the chip.

With such a slow clock speed, and some kind of layout or bypassing
issue, it's entirely possible you're getting a hiccup of a few hundred
ns on one of the clock edges, which is double-clocking the core. The
PIC18F series is faster than the older 16C series and will likely be
less tolerant of such things.


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

Posted by PigPOg on June 20th, 2006


On Tue, 20 Jun 2006 10:59:07 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

Spehro

The micro is on a SMD populated 4-layer PCB and Cext is connected
directly to VSS. In addition, there is a 100nF cap close to the micro
supply pins. I'm still investigating...

Regards,
Simon

Posted by Spehro Pefhany on June 20th, 2006


On Tue, 20 Jun 2006 16:19:30 +0100, the renowned PigPOg
<simon@capella.co.uk> wrote:

Okay, we can certainly rule that out. If you're not making a mistake
in your evaluation of the execution speed, it's almost looking like a
silicon problem. I doubt ext. RC clock is very often used with the 18F
series.

....when you have eliminated the impossible, whatever remains, however
improbable, must be the truth..


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

Posted by Robert Scott on June 20th, 2006


On Tue, 20 Jun 2006 14:56:42 +0100, PigPOg <simon@capella.co.uk> wrote:

I take it back. The PIC24H series is the one with the 2x clock. I think all
PIC18s have a 4x clock.


Robert Scott
Ypsilanti, Michigan

Posted by Roman Ziak on June 21st, 2006


PigPOg wrote:

Just curious, hos did you determine it was 2x speed ? It is exactly
twice or approximate ?

Btw. check errata for this chip, it seems it has several problems with
internal RC oscillator.

http://www.microchip.com/stellent/id...t=PIC18F1 320

Roman

Posted by PigPOg on June 22nd, 2006


On Tue, 20 Jun 2006 22:40:42 -0400, Roman Ziak <news12@ziak.com>
wrote:

Roman, thanks for the reply. I double checked with a small delay
routine on the 16c54 and 18f1320 and it is exactly 2x speed. Thanks
for the errata link, I'll investigate further.

Regards,
Simon

Posted by PigPOg on June 22nd, 2006


On Tue, 20 Jun 2006 11:25:07 +0100, PigPOg <simon@capella.co.uk>
wrote:

Gulp! How embarrassing. There's an error in code migration. Fixed now,
sorry to bother everyone - must re-check thoroughly next time before
posting.

Thanks all,
Simon


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