"David Brown" <david@no.westcontrol.spam.com> wrote in message news:<bhqq3m$6jv$1@news.netpower.no>...

Typical RS-232 asynchronous serial communications require that each
side's clock is accurate to within 2% of the nominal data rate. The
receiver syncs up his clock at the leading edge of the start bit, but
never resyncs during the frame. The receiver then tries to sample the
remainder of the frame in the center of each bit. Assuming the sender
and receiver are both off 2%, but in different directions, the
receiver would be about 42% of a bit width off center by the time he
got to the first stop bit on an 8-bit+parity "frame." IOW, just about
ready to fall off the bit entirely.

Robert Wessel wrote:
All of the replies so far have ignored the slew rate limiting in the
line
drivers. The effect of these at 115200 bps is that an appreciable
amount
of each bit time will be consumed by a possible change of state, mark ->
space or space -> mark. If the final bit time is off by 42%, there is a
very high probability that it will sample during a change of state.
Behavior of the line driver is probably undefined during this time
period,
and is likely to produce erratic behavior.

To see what I'm talking about, hook a scope to the Tx line of a serial
port
transmitting at 115200 bps. Send a continuous stream of 'u's, which
have
a transition between each pair of bits. The tops and bottoms of the
bits
almost don't flatten out before the end of the bit time. Compare that
to
the same data transmitted at a much lower data rate. Peaks are
comparitively
flatter.

Just one of those darn real-world analog phenomena.
--- rod.