Hi,

I have a question about Makefile variable.

Is there a way to declare a Makefile variable, which I use in my C program
(possibly via #ifdef compiler directive)? I know that I can declare such
a variable in a .h file via #def directive, and refer to it in my C
program.

But I would like use Makefile instead of header file, since I do not want
to edit my code.

Thanks,

- Vinayak

On Fri, 20 Jan 2006 10:23:08 -0500, Vinayak Naik wrote:
Most C compilers will let you define preprocessor symbols on the command
line, which you can easily arrange to do in a Makefile. For example, gcc
uses the syntax:

gcc -DSYMBOL=value foo.c

to do the equivalent of

#define SYMBOL value

in your program. Many other C compilers also use this convention,
although it's not part of any standard.



--
Dave Seaman
U.S. Court of Appeals to review three issues
concerning case of Mumia Abu-Jamal.
<http://www.mumia2000.org/>